In this chapter, you will create an intellectual property (IP) using the Create and Package New IP wizard. You will also design a system to include the new IP created for the Xilinx® Zynq®-7000 SoC device.

For the IP, you will develop a Linux-based device driver as a module that can be dynamically loaded onto the running kernel.

You will also develop Linux-based application software for the system to execute on the Zynq SoC ZC702 board.

Important

You will need to rebuild the Linux kernel: a Linux host machine to run PetaLinux is required.

Example 11: Creating Peripheral IP: Creating Peripheral IP

Example 12: Device Driver Development: Device Driver Development

Example 13: Loading a Module into a Kernel and Executing the Application: Loading the Module into a Kernel and Executing the Application

In this section, you will create an AXI4-Lite compliant slave peripheral IP framework using the Create and Package New IP wizard. You will also add functionality and port assignments to the peripheral IP framework.

The peripheral IP you will create is an AXI4-Lite compliant slave IP. It includes a 28-bit counter. The four most significant bits of the counter drive the four output ports of the peripheral IP. The block diagram is shown in the following figure.

Custom IP Structure¶

The block diagram includes the following configuration register:

Register Name

Control Register

Relative Address

0x0000_0000

Width

1-bit

Access Type

Read/Write

Description

Start/Stop the Counter

Field Name

Bits

Type

Reset Value

Description

Control

Bit 0

R/W

0x0

1 : Start Counter 2 : Stop Counter

In this section, you will create an AXI4-Lite compliant slave peripheral IP.

Create a new project as described in Creating a New Embedded Project with Zynq SoC.

With the Vivado design open, select Tools → Create and Package New IP. Click Next to continue.

Select Create a new AXI4 peripheral and then click Next.

Fill in the peripheral details as follows:

Screen

System Property

Setting or Comment to Use

Peripheral Details

Name

Blink

Version

1.0

Display name

Blink_v1.0

Description

My new AXI IP

IP location

C:/designs/ip_repro

Overwrite

existing unchecked

Click Next.

In the Add Interfaces page, accept the default settings and click Next.

In the Create Peripheral page, select Edit IP and then click Finish. Upon completion of the new IP generation process, the Package IP window opens (see the following figure).

In the Hierarchy view of the Sources window, right-click blink_v1_0 under the Design Sources folder and select Open File. You need to add Verilog code that creates output ports to map to the external LEDs on the ZC702 board. Navigate to the line //Users to add ports here and add output wire \[3:0\] ledsbelow this line, as shown in the following example:

Find the instantiation to the AXI bus interface and add .leds(leds), as shown in the following example, to map the port connections:

Save and close blink_v1_0.v.

Under Sources → Hierarchy → Design Sources→ blink_v1_0, right-click blink_v1_0_S00_AXI_inst - blink_v1_0_S00_AXI and select Open File.

Next, you will need to add Verilog code that creates output ports to map to the external LEDs on the ZC702 board and also create the logic code to blink the LEDs when register 0 is written to.

Navigate to the line //Users to add ports here and add output wire \[3:0\] leds below this line, as shown in the example below:

Find the AXI4-Lite signals section:

After this section, add a custom register, which you will use as a counter. Add the following code:

Find the I/O connections assignments section:

Add the following code at the bottom:

Toward the bottom of the file, find the section that states Add user logic here. Add the following code, which will increment the count while the slv_reg0 is set to 0x1. If the register is not set, the counter will not increment.